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CXP85840A/85848A/85856A
CMOS 8-bit Single Chip Microcomputer
Description The CXP85840A/85848A/85856A are the CMOS 8-bit microcomputer integrating on a single chip an A/D converter, serial interface, timer/counter, time-base timer, closed caption decoder, data slicer, on-screen display function, I2C bus interface, PWM output, remote control reception circuit, HSYNC counter and watchdog timer, besides the basic configurations of 8-bit CPU, ROM, RAM, I/O ports. The CXP85840A/85848A/85856A also provide a power-on reset function and sleep function that enables to lower the power consumption. 64 pin SDIP (Plastic) 64 pin QFP (Plastic)
Structure Features Silicon gate CMOS IC * A wide instruction set (213 instructions) which covers various types of data - 16-bit operation/multiplication and division/Boolean bit operation instructions * Minimum instruction cycle 333ns at 12MHz operation * Incorporated ROM 40K bytes (CXP85840A) 48K bytes (CXP85848A) 56K bytes (CXP85856A) * Incorporated RAM 2176 bytes (Excludes closed caption decoder and VRAM for on-screen display) * Peripheral functions - A/D converter 8-bit 6-channel successive approximation method (Conversion time of 26.7s at 12MHz) - Serial interface 8-bit clock sync type, 1 channel - Timer 8-bit timer 8-bit timer/counter 19-bit time-base timer - Closed caption decoder Data slicer Corresponds to FCC (EDS supported), 8 x 13 dots, 192 character types 15 character colors, 4 lines x 34 characters frame background 15 colors/ half blanking italic, underline, vertical scrolling - On-screen display (OSD) function 12 x 16 dots, 192 character types, 15 character colors 2 lines x 24 characters frame background 8 colors/ half blanking background on full screen 15 colors/ half blanking edging and vertical scrolling for every line jitter elimination circuit sprite OSD, 12 x 16 dots, 1 screen, 8 colors for every dot - I2C bus interface - PWM output 8 bits, 8 channels - Remote control reception circuit 8-bit pulse measurement counter, 6-stage FIFO - HSYNC counter 2 channels - Watchdog timer * Interruption 15 factors, 15 vectors, multi-interruption possible * Standby mode Sleep * Package 64-pin plastic SDIP/QFP * Piggyback/evaluator CXP85890A 64-pin ceramic PSDIP (Supports custom font)
Perchase of Sony's I2C components conveys a licence under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specifications as defined by Philips.
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
-1-
E97739A86
Block Diagram
XTAL RST MP VDD Vss INT0 INT1 INT2 EXTAL
LFC1
VIN SPC700 CPU CORE
8
LFC2 Cap
DATA SLICER CLOCK GENERATOR/ SYSTEM CONTROL PA0 to PA7
PORT A
7
CC DECODER
CVDD CVss
2
XLC EXLC R G 3 2 ROM 40K/48K/56K BYTES RAM 2176 BYTES
INTERRUPT CONTROLLER
ON SCREEN DISPLAY
PORT B
PB0 to PB6
B I YS YM HSYNC
VSYNC PRESCALER/ TIME BASE TIMER
PORT C
8
PC0 to PC7
RMC FIFO
REMOCON
PORT E
HSC0
HSYNC COUNTER 0
HSC1
HSYNC COUNTER 1
I2C BUS INTERFACE UNIT
8BIT PWM
AN0 to AN5
6
A/D CONVERTER
8
SCL0
SDA0
SDA1
SCL1
PORT F
PWM0 to PWM7
-2-
WATCHDOG TIMER
SI SO SCK
SERIAL INTERFACE UNIT
EC
8BIT TIMER/COUNTER 0
PORT D
8
PD0 to PD7
3
PE0 to PE2
TO
8BIT TIMER 1
8
PF0 to PF7
CXP85840A/85848A/85856A
CXP85840A/85848A/85856A
Pin Assignment (Top View) 64-pin SDIP
PC3 PC2 PC1 PC0 EC/PD7 RMC/PD6 HS1/PD5 HS0/PD4 SI/ PD3 SO/PD2 SCK/PD1 INT2/PD0 HSYNC/PA7 VSYNC/PA6 RST Vss XTAL EXTAL PA5/AN5 PA4/AN4 PA3/AN3 PA2/AN2 PA1/AN1 PA0/AN0 CVss LFC2 LFC1 VIN CVDD Cap INT1/PB6 PB5
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
PC4 PC5 PC6 PC7 PF0/PWM0 PF1/PWM1 PF2/PWM2 PF3/PWM3 PF4/SCL0/PWM4 PF5/SCL1/PWM5 PF6/SDA0/PWM6 PF7/SDA1/PWM7 PE0/TO PE1 PE2/INT0 MP Vss VDD NC EXLC XLC YM YS I B G R PB0 PB1 PB2 PB3 PB4
Note) 1. NC (Pin 46) is always connected to VDD. 2. Vss (Pins 16 and 48) are both connected to GND. 3. MP (Pin 49) is always connected to GND.
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CXP85840A/85848A/85856A
Pin Assignment (Top View) 64-pin QFP
PC0
64 63 62 61 60 59 58 57 56 55 54 53 52 HS1/PD5 HS0/PD4 SI/PD3 SO/PD2 SCK/PD1 INT2/PD0 HSYNC/PA7 VSYNC/PA6 RST Vss XTAL EXTAL PA5/AN5 PA4/AN4 PA3/AN3 PA2/AN2 PA1/AN1 PA0/AN0 CVss 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 PF3/PWM3 PF4/SCL0/PWM4 PF5/SCL1/PWM5 PF6/SDA0/PWM6 PF7/SDA1/PWM7 PE0/TO PE1 PE2/INT0 MP Vss VDD NC EXLC XLC YM YS I B G
PC2
PC4
PB4
PF0/PWM0
PD6/RMC
LFC1
PB0
PF1/PWM1
PD7/EC
PC5
PC6
PC7
PB3
LFC2
CVDD
Note) 1. NC (Pin 40) is always connected to VDD. 2. Vss (Pins 10 and 42) are both connected to GND. 3. MP (Pin 43) is always connected to GND.
INT1/PB6
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PB5
PB2
PB1
Cap
VIN
R
PF2/PWM2
PC1
PC3
CXP85840A/85848A/85856A
Pin Description Symbol PA0/AN0 to PA5/AN5 PA6/VSYNC PA7/HSYNC PB0 to PB5 PB6/INT1 I/O I/O/ Analog input I/O/Input I/O/Input I/O I/O/Input (Port A) 8-bit I/O port. I/O can be set in a unit of single bits. (8 pins) Description Analog inputs to A/D converter. (6 pins) OSD display vertical sync signal input. OSD display horizontal sync signal input.
(Port B) 7-bit I/O port. I/O can be set in a unit of single bits. (7 pins) External interruption request input. Active at the falling edge. (Port C) 8-bit I/O port. I/O can be set in a unit of single bits. (8 pins) External interruption request input. Active at the falling edge. (Port D) 8-bit I/O port. I/O can be set in a unit of single bits. Can drive 12mA synk current. (8 pins) Serial clock I/O. Serial data output. Serial data input. HSYNC counter (CH0) input. HSYNC counter (CH1) input. Remote control reception circuit input. External event input for timer/counter. (Port E) 3-bit I/O port. I/O can be set in a unit of single bits. (3 pins) (Port F) 8-bit output port and large current (12mA) N-channel open drain output. Lower 4 bits are medium drive voltage (12V); upper 4 bits are 5V drive. (8 pins) Rectangular wave output for timer/counter
PC0 to PC7
I/O
PD0/INT2 PD1/SCK PD2/SO PD3/SI PD4/HS0 PD5/HS1 PD6/RMC PD7/EC PE0/TO PE1 PE2/INT0 PF0/PWM0 to PF3/PWM3 PF4/SCL0/PWM4 PF5/SCL1/PWM5 PF6/SDA0/PWM6 PF7/SDA1/PWM7 R, G, B, I, YS, YM
I/O/Input I/O/I/O I/O/Output I/O/Input I/O/Input I/O/Input I/O/Input I/O/Input I/O/Output I/O I/O/Input
External interruption request input. Active at the falling edge. 8-bit PWM output. (8 pins)
Output/Output
Output/I/O
I2C bus interface transfer clock I/O. (2 pins) I2C bus interface transfer data I/O. (2 pins)
Output/I/O Output
6-bit OSD display output. (6 pins)
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CXP85840A/85848A/85856A
Symbol EXLC XLC VIN Cap LFC1, LFC2 CVDD CVss EXTAL XTAL RST MP NC VDD Vss Input Input
I/O
Description OSD display clock oscillation I/O. Oscillation frequency is determined by the external L and C. External composite video signal input. Input the 2Vp-p signal via a capacitor.
Output Input -- --
Connects a data slicer capacitor between Cap and CVss. Connects a low-pass filter capacitor for PLL circuit between LFC1 and LFC2. Positive power supply for data slicer. GND for data slicer. Connects a crystal for system clock oscillation. When a clock is supplied externally, input it to EXTAL and leave XTAL open. System reset; active at Low level. I/O pin. Outputs a Low level when the power is turned on and the internal power-on reset function operates. (Mask option) Test mode pin. Always connect to GND. No connected. Under normal operation, connect to VDD. Positive power supply. GND. Connect two Vss pins to GND.
Output I/O Input
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CXP85840A/85848A/85856A
Input/Output Circuit Formats for Pins Pin Port A
Port A data
Circuit format
When reset
Port A direction
PA0/AN0 to PA5/AN5
IP
"0" when reset Data bus RD (Port A) Port A function selection "0" when reset A/D converter
Input protection circuit
Hi-Z
6 pins Port A
Input multiplexer
Port A data Port A direction "0" when reset IP
PA6/VSYNC PA7/HSYNC
Data bus RD (Port A)
Hi-Z
Schmitt input
VSYNC, HSYNC Input polarity
2 pins Port B Port C
Ports B, C data
"0" when reset
PB0 to PB5 PB6/INT1 PC0 to PC7
Data bus
Ports B, C direction "0" when reset
IP
Hi-Z
RD (Ports B, C) Schmitt input INT1
15 pins
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CXP85840A/85848A/85856A
Pin Port D
Circuit format
When reset
Port D data
PD0/INT2 PD3/SI PD4/HS0 PD5/HS1 PD6/RMC PD7/EC
Port D direction "0" when reset
IP
Hi-Z
Schmitt input
Data bus RD (Port D)
6 pins
INT2, SI, HS0, HS1, RMC, EC
Large current 12mA
Port D
SCK, SO Serial output enable
PD1/SCK PD2/SO
Port D data
Port D direction "0" when reset Data bus Schmitt input
IP
Hi-Z
RD (Port D)
2 pins Port E
SCK only
Large current 12mA
TO Port E function selection "1" when reset
PE0/TO PE1 PE2/INT0
Port E data "1" when reset for PE0 and 1 Port E direction "1" when reset for PE0 and 1 "0" when reset for PE2 Data bus RD (Port E) IP
PE0, PE1: High level PE2: Hi-Z
Schmitt input only for PE2
3 pins
INT0
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CXP85840A/85848A/85856A
Pin Port F
PWM0 to PWM3
Circuit format
When reset
PF0/PWM0 to PF3/PWM3
Port F data "1" when reset Port F function selection 12V drive voltage Large current 12mA
Hi-Z
4 pins Port F
"0" when reset
SCL, SDA I2C output enable
PF4/PWM4/SCL0 PF5/PWM5/SCL1 PF6/PWM6/SDA0 PF7/PWM7/SDA1
PWM4 to PWM7
Port F data "1" when reset Port F function selection "0" when reset Schmitt input
IP
Hi-Z
BUS SW To other I2C pins (SCL1 for SCL0) Large current 12mA
4 pins
SCL, SDA (I2C circuit)
R G B I YS YM 6 pins
R, G, B, I, YS, YM
Output polarity "0" when reset Writing data to output polarity register brings output to active.
Hi-Z
EXLC XLC
EXLC
IP
Oscillation control
Oscillation halted
XLC IP OSC display clock
2 pins
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CXP85840A/85848A/85856A
Pin
Circuit format
* Diagram shows the circuit composition during oscillation.
When reset
EXTAL XTAL
EXTAL
IP
* Feedback resistor is removed during stop mode. (This device does not enter the stop mode.)
Oscillation
2 pins
XTAL
Pull-up resistor
RST
OP Mask option
Schmitt input
Low level
1 pin
From power-on reset circuit (Mask option)
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CXP85840A/85848A/85856A
Absolute Maximum Ratings Item Supply voltage Input voltage Output voltage Medium drive output voltage High level output current High level total output current Symbol VDD VIN VOUT VOUTP IOH IOH IOL Low level output current IOLC Low level total output current Operating temperature Storage temperature Allowable power dissipation IOL Topr Tstg PD 20 100 -20 to +75 -55 to +150 1000 600 mA mA C C mW mW SDIP-64P-01 GFP-64P-L01 Ratings -0.3 to +7.0 -0.3 to +7.01 -0.3 to +7.01 -0.3 to +15.0 -5 -50 15 Unit V V V V mA mA mA PF0 to PF3 pins
(Vss = 0V reference) Remarks
Total of all output pins Ports excluding large current outputs (value per pin) Large current output ports (value per pin2) Total of all output pins
1 VIN and VOUT should not exceed VDD + 0.3V. 2 The large current output port is Port D (PD) and Port F (PF). Note) Usage exceeding absolute maximum ratings may permanently impair the LSI. Normal operation should be conducted under the recommended operating conditions. Exceeding those conditions may adversely affect the reliability of the LSI. Recommended Operating Conditions Item Symbol Min. 4.5 Supply voltage VDD 3.5 2.5 Data slicer supply voltage CVDD VIH High level input voltage VIHS VIHEX VIL Low level input voltage VILS VILEX Operating temperature 1 2 3 4 5 Topr 4.5 0.7VDD 0.8VDD Max. 5.5 5.5 5.5 5.5 VDD VDD Unit V V V V V V V V V V C (Vss = 0V reference) Remarks Guaranteed operation range for 1/2 and 1/4 frequency dividing clocks Guaranteed operation range for 1/16 frequency dividing clock or sleep mode Guaranteed data hold range for stop mode1 5 2 3 EXTAL pin4 2 3 EXTAL pin4
VDD - 0.4 VDD + 0.3 0 0 -0.3 -20 0.3VDD 0.2VDD 0.4 +75
This device does not enter the stop mode. PA, PB, PC, PE0 to PE1, SCL0 to 1, SDA0 to 1 pins. INT2, SCK, SO, SI, HS0, HS1, RMC, EC, INT1, HSYNC, VSYNC, RST pins. Specifies only during external clock input. CVDD and VDD should be set to the same voltage. - 11 -
CXP85840A/85848A/85856A
Electrical Characteristics DC characteristics Item High level output voltage Symbol VOH Pins PA to PD, PE R, G, B, I, YS, YM PA to PD, PE R, G, B, I, YS, YM, PF0 to PF3, RST1 Low level output voltage VOL PD, PF PF4 to PF7 (SCL0, SCL1, SDA0, SDA1) IIHE Input current IIHL IILR I/O leakage current Open drain I/O leakage current (in N-ch Tr OFF state) IIZ RST2 PA to PE, HSYNC, VSYNC, R, G, B, I, YS, YM, RST2 PF0 to PF3 ILOH PF4 to PF7 SCL0: SCL1 SDA0: SDA1 EXTAL
(Ta = -20 to +75C, Vss = 0V reference) Conditions VDD = 4.5V, IOH = -0.5mA VDD = 4.5V, IOH = -1.2mA VDD = 4.5V, IOL = 1.8mA VDD = 4.5V, IOL = 3.6mA VDD = 4.5V, IOL = 12.0mA VDD = 4.5V, IOL = 3.0mA VDD = 4.5V, IOL = 4.0mA VDD = 5.5V, VIH = 5.5V VDD = 5.5V, VIL = 0.4V VDD = 5.5V, VIL = 0.4V VDD = 5.5V, VI = 0, 5.5V VDD = 5.5V, VOH = 12.0V VDD = 5.5V, VOH = 5.5V VDD = 4.5V VSCL0 = VSCL1 = 2.25V VSDA0 = VSDA1 = 2.25V 1/2 frequency dividing clock operation VDD = 5.5V, 12MHz crystal oscillation (C1 = C2 = 15pF) VDD3 Sleep mode VDD = 5.5V, 12MHz crystal oscillation (C1 = C2 = 15pF) Stop mode4 VDD = 5.5V, termination of 12MHz oscillation CVDD VDD = 5.5V -- -- 0.5 -0.5 -1.5 Min. 4.0 3.5 0.4 0.6 1.5 0.4 0.6 40 -40 -400 10 50 10 120 Typ. Max. Unit V V V V V V V A A A A A A
I2C bus switch connection impedance RBS (in output Tr OFF state)
IDD
37
50
mA
Supply current
IDDSL
2.5
5
mA
IDDST ICVDD Input capacitance CIN
-- 5.0 10
-- 10.0 20
A mA pF
PA to PE, SCL, Clock 1MHz SDA, EXLC, EXTAL, 0V for no-measured pins VIN, RST
1 Specifies RST pin only when the power-on reset circuit is selected with mask option. 2 For RST pin, specifies the input current when pull-up resistor is selected, and specifies the leakage current when non-resistor is selected. 3 When all output pins are left open. Specifies only when the OSD oscillation is halted. 4 This device does not enter the stop mode.
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CXP85840A/85848A/85856A
AC Characteristics (1) Clock timing Item System clock frequency System clock input pulse width System clock input rise and fall times Event count input clock pulse width Event count input clock rise and fall times Symbol fC Pins XTAL EXTAL EXTAL
(Ta = -20 to +75C, VDD = 4.5 to 5.5V, Vss = 0V reference) Conditions Fig. 1, Fig. 2 Fig. 1, Fig. 2 External clock drive Fig. 1, Fig. 2 External clock drive Fig. 3 Min. Typ. 12.0 37.5 Max. Unit MHz ns
tXL, tXH tCR, tCF tEH, tEL tER, tEF
EXTAL EC
200
ns
tsys1 + 50
20
ns
EC
Fig. 3
ms
1 Indicates three values according to the contents of the clock control register (CLC: 00FEh) upper 2 bits (CPU clock selection). tsys (ns) = 2000/fc (Upper 2 bits = "00"), 4000/fc (Upper 2 bits = "01"), 16000/fc (Upper 2 bits = "11")
Fig. 1. Clock timing
1/fc
VDD - 0.4V EXTAL 0.4V tXH tCF tXL tCR
Fig. 2. Clock applied conditions
Crystal oscillation Ceramic oscillation External clock
EXTAL C1
XTAL C2
EXTAL
XTAL
OPEN
Fig. 3. Event count clock timing
0.8VDD EC 0.2VDD tEH tEF tEL tER
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CXP85840A/85848A/85856A
(2) Serial transfer Item SCK cycle time SCK High and Low level widths SI input setup time (for SCK ) SI hold time (for SCK ) SCK SO delay time Symbol Pins SCK
(Ta = -20 to +75C, VDD = 4.5 to 5.5V, Vss = 0V reference) Conditions Input mode Output mode SCK SCK input mode SCK output mode SI SCK input mode SCK output mode SI SCK input mode SCK output mode SO SCK input mode SCK output mode Min. 1000 8000/fc 400 4000/fc - 50 100 200 200 100 200 100 Max. Unit ns ns ns ns ns ns ns ns ns ns
tKCY tKH tKL tSIK tKSI tKSO
Note) The load of SCK output mode and SO output delay time is 50 pF + 1TTL.
Fig. 4. Serial transfer timing
tKCY tKL tKH
0.8VDD SCK 0.2VDD
tSIK
tKSI
0.8VDD SI Input data 0.2VDD
tKSO
0.8VDD SO 0.2VDD Output data
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CXP85840A/85848A/85856A
(3) A/D converter Item Resolution Linearity error Zero transition voltage Full-scale transition voltage Conversion time Sampling time Analog input voltage VZT1 VFT2 Symbol Pins
(Ta = -20 to +75C, VDD = 4.5 to 5.5V, Vss = 0V reference) Conditions Min. Typ. Max. 8 3 Ta = 25C VDD = 5.0V Vss = 0V -10 4910 160/fADC3 12/fADC3 AN0 to AN5 0 VDD 10 4970 70 5030 Unit Bits LSB mV mV s s V
tCONV tSAMP
VIAN
Fig. 5. Definitions of A/D converter terms
FFh FEh
Linearity error
1 VZT: Value at which the digital conversion value changes from 00H to 01H and vice versa. 2 VFT: Value at which the digital conversion value changes from FEh to FFh and vice versa. 3 fADC indicates the below values due to the contents of bit 6 (CKS) of the A/D control register (ADC: 00F9h) and bits 7 (PCK1) and 6 (PCK0) of the clock control register (CLC: 00FEh). CKS PCK1, 0 00 ( = fEX/2) 01 ( = fEX/4) 11 ( = fEX/16) 0 (/2 selection) fADC = fC/2 fADC = fC/4 fADC = fC/16 1 ( selection) fADC = fC fADC = fC/2 fADC = fC/8
Digital conversion value
01h 00h
VZT Analog input
VFT
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CXP85840A/85848A/85856A
(4) Interruption, reset input (Ta = -20 to +75C, VDD = 4.5 to 5.5V, Vss = 0V reference) Item External interruption High and Low level widths Reset input Low level width Symbol Pins INT0 INT1 INT2 RST Conditions Min. 1 32/fc Max. Unit s s
tIH tIL tRSL
Fig. 6. Interruption input timing
tIH INT0 INT1 INT2 (falling edge) tIL
0.8VDD 0.2VDD
Fig. 7. RST input timing
tRSL
RST 0.2VDD
(5) Power-on reset1 Item Power supply rise time Symbol Pins VDD
(Ta = -25 to +75C, Vss = 0V reference) Conditions Power-on reset Repeated power-on reset Min. 0.05 1 Max. 50 Unit ms ms
tR Power supply cut-off time tOFF
1 Specifies only when the power-on reset function is selected.
Fig. 8. Power-on reset
VDD
4.5V 0.2V 0.2V
tR Take care when turning the power on.
tOFF
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CXP85840A/85848A/85856A
(6) I2C bus timing Item SCL clock frequency Bus-free time before starting transfer Hold time for starting transfer Clock Low level width Clock High level width Setup time for repeated transfers Data hold time Data setup time SDA, SCL rise time SDA, SCL fall time Setup time for transfer completion Symbol fSLC
(Ta = -20 to +75C, VDD = 4.5 to 5.5V, Vss = 0V reference) Pins SCL SDA, SCL SDA, SCL SCL SCL SDA, SCL SDA, SCL SDA, SCL SDA, SCL SDA, SCL SDA, SCL 4.7 Conditions Min. 0 4.7 4.0 4.7 4.0 4.7 01 250 1 300 Max. 100 Unit kHz s s s s s s ns s ns s
tBUF tHD; STA tLOW tHIGH tSU; STA tHD; DAT tSU; DAT tR tF tSU; STO
1 The data hold time should be 300ns or more because the SCL rise time (300ns Max.) is not included in it.
Fig. 9. I2C bus transfer timing
SDA tBUF tR tF tHD; STA
SCL tHD; STA tSU; STA P S tLOW tHD; DAT tHIGH tSU; DAT St tSU; STO P
Fig. 10. I2C bus device recommended circuit
I2C device RS SDA0 (or SDA1) SCL0 (or SCL1) RS RS
I2C device RS RP RP
* A pull-up resistor (Rp) must be connected to SDA0 (or SDA1) and SCL0 (or SCL1). * The SDA0 (or SDA1) and SCL0 (or SCL1) series resistance (Rs = 300 or less) can be used to reduce the spike noise caused by CRT flashover.
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CXP85840A/85848A/85856A
(7) OSD timing Item OSD clock frequency HSYNC pulse width VSYNC pulse width HSYNC after-write rise and fall times VSYNC before-write rise and fall times * H indicates 1HSYNC period.
(Ta = -20 to +75C, VDD = 4.5 to 5.5V, Vss = 0V reference) Symbol fOSC Pins EXLC XLC HSYNC VSYNC HSYNC VSYNC Conditions Fig. 12 Fig. 11 Fig. 11 Fig. 11 Fig. 11 Min. 4 1.2 1 200 1.0 Max. 16.5 Unit MHz s H* ns s
tHWD tVWD tHCG tVCG
Fig. 11. OSD timing
tHWD tHCG
HSYNC For OSD I/O polarity register (OPOL: 01FDh) bit 7 at "0"
0.8VDD
0.2VDD
tVCG
tVWD 0.8VDD
VSYNC For OSD I/O polarity register (OPOL: 01FDh) bit 6 at "0"
0.2VDD
Fig. 12. LC oscillation circuit connection
EXLC
XLC R1 L
C1
C2
1 The XLC series resistor can reduce the frequency of occurrence of the undesired radiation.
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CXP85840A/85848A/85856A
(8) Data slicer external circuit Item VIN pin coupling capacitance Symbol CVIN Pin VIN Min.
(Ta = -20 to +75C, VDD = 4.5 to 5.5V, Vss = 0V reference) Typ. 0.1 Max. Unit F Remarks The B characteristics or more of temperature characteristics is recommended. The B characteristics or more of temperature characteristics is recommended. The B characteristics or more of temperature characteristics is recommended.
Cap pin capacitance Ccap
Cap
4700
pF
PLL low-pass filter capacitance Composite video signal input
CLPF
LFC1, LFC2
0.47
F
Video In VIN
2.0
Vp-p
Fig. 13. Data slicer external recommended circuit
5.0V
CVDD LFC2 CLPF LFC1 R1 CVIN VIN Video In C1 R2
Cap Ccap CVss
[Recommended Constant] R1 = 220 (error: 5%; allowable power dissipation: 1/8W or more) R2 = 1M (error: 5%; allowable power dissipation: 1/8W or more) C1 = 1200pF (ceramic), the B characteristics or more of temperature characteristics is recommended.
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CXP85840A/85848A/85856A
Appendix Fig. 14. SPC 700 Series recommended oscillation circuit (i)
EXTAL
XTAL Rd
C1
C2
Manufacture RIVER ELETEC CO., LTD. KINSEKI LTD.
Model HC-49/U03 HC-19/U (-S)
fc (MHz) 12.0 12.0
C1 (pF) 5 15
C2 (pF) 5 15
Rd () 01 01
Circuit example (i) (i)
1 The XTAL series resistor can reduce the effect of the noise caused by the electrostatic discharge.
Mask Option Table Item Reset pin pull-up resistor Power-on reset circuit Content Non-existent Non-existent Existent Existent
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CXP85840A/85848A/85856A
Fig. 15. Characteristic curves
IDD vs. VDD
(fc = 12MHz, Ta = 25C, Typical) 100 1/2 dividing mode 1/4 dividing mode 40 50
IDD vs. fc
(VDD = 5V, Ta = 25C, Typical)
45 1/2 dividing mode
IDD - Supply current [mA]
1/16 dividing mode
35
IDD - Supply current [mA]
10
30
25
1/4 dividing mode
Sleep mode 1
20
15
10
1/16 dividing mode
5
Sleep mode
0 0.1 3 4 5 6 VDD - Supply voltage [V]
4
8 fc - System clock [MHz]
12
16
Parameter curve for OSD oscillation L vs. C
(theoretically calculated value) 100
L - Inductance [H]
10
10MHz 12MHz 14MHz 16MHz fOSC = 0 1 2 LC 50 C1, C2 - Capacitance [pF] C = C1 // C2 100
- 21 -
CXP85840A/85848A/85856A
Package Outline
Unit: mm
64PIN SDIP (PLASTIC) 750mil
+ 0.4 57.6 - 0.1 64 33
19.05 + 0.3 17.1 - 0.1
+ 0.1 0.05 0.25 -
0 to 15 32 0.5 0.1 0.9 0.15
1 1.778
PACKAGE STRUCTURE
MOLDING COMPOUND SONY CODE EIAJ CODE JEDEC CODE SDIP-64P-01 SDIP064-P-0750-A LEAD TREATMENT LEAD MATERIAL PACKAGE WEIGHT EPOXY / PHENOL RESIN SOLDER PLATING 42 ALLOY 8.6g
64PIN QFP(PLASTIC)
23.9 0.4 + 0.4 20.0 - 0.1
51 33
3 MIN
0.5 MIN + 0.4 4.75 - 0.1
+ 0.1 0.15 - 0.05 0.15
52
32
17.9 0.4
+ 0.4 14.0 - 0.1
64
20
+ 0.2 0.1 - 0.05
1 1.0 + 0.15 0.4 - 0.1
+ 0.35 2.75 - 0.15 0.12 M
PACKAGE STRUCTURE
PACKAGE MATERIAL SONY CODE EIAJ CODE JEDEC CODE QFP-64P-L01 QFP064-P-1420 LEAD TREATMENT LEAD MATERIAL PACKAGE MASS EPOXY RESIN SOLDER/PALLADIUM PLATING 42/COPPER ALLOY 1.5g
- 22 -
0.8 0.2
19
16.3

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